The microcomputer according to the invention is based on a microcomputer of the generic type of the main claim. Data Sheet MC 68 F 333 TS/D, Motorola 1992, already discloses a microcomputer which has, apart from the central processing unit, a programmable, non-volatile memory (flash EEPROM), input/output components, a monitoring circuit (watchdog timer), and also a volatile memory (code RAM), into which there can be written program data which can be accessed by the instruction counter of the central processing unit. All the said components are integrated on a chip. The microcomputer is configured such that it can both access program data which are located in the programmable, non-volatile memory and can execute a program which is located in the volatile memory. In both cases, the monitoring circuit is activated, ie. it must be ensured that, in the case of regular program flow, the monitoring circuit is reset at the correct time, since otherwise the monitoring circuit carries out a resetting of the microcomputer. A disadvantage of this microcomputer is that haphazard changes of the memory content in the volatile memory (for example due to interfering EMC radiation) can cause the forming a situation in which the monitoring circuit is reset at the correct time although the program flow is irregular.